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02606nam a2200601 4500 |
| 001 |
ocn870263361 |
| 003 |
OCoLC |
| 005 |
20170124071657.6 |
| 006 |
m o d |
| 007 |
cr cnu|||unuuu |
| 008 |
140210s2014 enk ob 001 0 eng d |
| 040 |
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|a DG1
|b eng
|e rda
|e pn
|c DG1
|d YDXCP
|d E7B
|d UMC
|d OCLCF
|d OCLCQ
|d COO
|d OCLCQ
|d DEBBG
|d GrThAP
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| 019 |
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|a 961590770
|a 962707582
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| 020 |
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|a 9781118790137
|q (electronic bk.)
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| 020 |
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|a 1118790138
|q (electronic bk.)
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| 020 |
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|a 9781118790229
|q (electronic bk.)
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| 020 |
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|a 1118790227
|q (electronic bk.)
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| 020 |
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|a 9781848215931
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| 020 |
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|a 1848215932
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| 024 |
7 |
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|a 10.1002/9781118790229
|2 doi
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| 029 |
1 |
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|a CHNEW
|b 000694615
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| 029 |
1 |
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|a CHNEW
|b 000694619
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| 029 |
1 |
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|a NZ1
|b 15495716
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| 029 |
1 |
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|a DEBBG
|b BV043396544
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| 029 |
1 |
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|a CHVBK
|b 374456720
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| 029 |
1 |
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|a CHNEW
|b 000886753
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| 035 |
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|a (OCoLC)870263361
|z (OCoLC)961590770
|z (OCoLC)962707582
|
| 050 |
|
4 |
|a QA76.54
|
| 082 |
0 |
4 |
|a 004.33
|2 23
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| 049 |
|
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|a MAIN
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| 100 |
1 |
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|a Rochange, Christine,
|e author.
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| 245 |
1 |
0 |
|a Time-predictable architectures /
|c Christine Rochange, Sascha Uhrig, Pascal Sainrat.
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| 264 |
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1 |
|a London, UK :
|b ISTE, Ltd. ;
|a Hoboken, NJ :
|b John Wiley & Sons, Inc.,
|c 2014.
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| 264 |
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4 |
|c ©2014
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| 300 |
|
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|a 1 online resource.
|
| 336 |
|
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|a text
|b txt
|2 rdacontent
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| 337 |
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|a computer
|b c
|2 rdamedia
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| 338 |
|
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|a online resource
|b cr
|2 rdacarrier
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| 490 |
1 |
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|a Focus series
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| 505 |
0 |
|
|a Real-Time Systems and Time Predictability / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Timing Analysis of Real-Time Systems / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Current Processor Architectures / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Memory Hierarchy / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Multicores / Christine Rochange, Sascha Uhrig, Pascal Sainrat -- Example Architectures / Christine Rochange, Sascha Uhrig, Pascal Sainrat.
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| 504 |
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|a Includes bibliographical references and index.
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| 588 |
0 |
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|a Print version record.
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| 650 |
|
0 |
|a Real-time data processing.
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| 650 |
|
0 |
|a Computer architecture.
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| 650 |
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7 |
|a Computer architecture.
|2 fast
|0 (OCoLC)fst00872026
|
| 650 |
|
7 |
|a Real-time data processing.
|2 fast
|0 (OCoLC)fst01091219
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| 655 |
|
4 |
|a Electronic books.
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| 700 |
1 |
|
|a Uhrig, Sascha,
|e author.
|
| 700 |
1 |
|
|a Sainrat, Pascal,
|e author.
|
| 776 |
0 |
8 |
|i Print version:
|a Rochange, Christine, author.
|t Time-predictable architectures
|z 9781848215931
|w (OCoLC)868374827
|
| 830 |
|
0 |
|a Focus series.
|
| 856 |
4 |
0 |
|u https://doi.org/10.1002/9781118790229
|z Full Text via HEAL-Link
|
| 994 |
|
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|a 92
|b DG1
|