Transactions on High-Performance Embedded Architectures and Compilers V

Transactions on High-Performance Embedded Architectures and Compilers V

Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on...

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Bibliographic Details
Corporate Author: SpringerLink (Online service)
Other Authors: Silvano, Cristina (Editor, http://id.loc.gov/vocabulary/relators/edt), Bertels, Koen (Editor, http://id.loc.gov/vocabulary/relators/edt), Schulte, Michael (Editor, http://id.loc.gov/vocabulary/relators/edt)
Format: Electronic eBook
Language:English
Published: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2019.
Edition:1st ed. 2019.
Series:Transactions on High-Performance Embedded Architectures and Compilers, 11225
Subjects:
Arithmetic and logic units, Computer.
Microprogramming .
Logic design.
Architecture, Computer.
Operating systems (Computers).
Programming languages (Electronic computers).
Arithmetic and Logic Structures.
Control Structures and Microprogramming.
Logic Design.
Computer System Implementation.
Operating Systems.
Programming Languages, Compilers, Interpreters.
Online Access:Full Text via HEAL-Link
Table of Contents:
  • Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards.-Programmable and Scalable Architecture for Graphics Processing Units
  • Circular Buffers with Multiple Overlapping Windows for Cyclic Task Graphs
  • A Hardware-Accelerated Estimation-Based Power Profiling Unit. - Enabling Early Power-Aware Embedded Software Design and On-Chip Power Management
  • The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors
  • Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability
  • A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design.

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